21-25 June 2021
Clarion Congress Hotel Prague
Europe/Prague timezone
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A high speed data link optimization for digitalized data transfer to processing FPGAs

Not scheduled
20m
3rd floor (Clarion Congress Hotel Prague)

3rd floor

Clarion Congress Hotel Prague

Freyova 945/33, 190 00 Prague 9 - Vysočany
Oral presentation 01 Fundamental Physics

Speaker

Dr COLLADO, Javier (Instituto de Física Corpuscular (IFIC) - CSIC / Universidad de Valencia - ETSE)

Description

State-of-the-art arrays of detectors, that require digital processing, may have a sizeable number of digitalized signal links. This is the case in several experimental nuclear physics instruments. Moreover, the sampled signals data rate, defined primary by the signal bandwidth of the individual detector, may not exhaust the capabilities of a single FPGA transceiver input.
This is a critical issue in position sensitive HPGe segmented detectors as AGATA, where each crystal detector has 36 segment signals plus a core signal. The 37 signals for each crystal detector are digitalized and processed with an independent electronics. The sampling is performed with 14 bit (about 12 ENOB) at 100MHz due to the bandwidth limitation to about 30 MHz of the detector and preamplifier response. Each ADC has a link to the preprocessing system at 2Gbps in a JESD204 protocol.
The preprocessing is carried out in a modern FPGA with transceiver data rate capabilities over 10Gbps. Moreover, cost effective FPGA have a limited number of transceivers for a given FPGA processing capabilities. The investigation of a cost-effective and efficient solution to the mismatch between both data rates, optimizing the use of the FPGA resources, is the topic of the present work.

We have developed a solution based on the Time Domain Multiplexing link aggregation, in the form of a Mezzanine board. This mezzanine combines four channels from an optical or copper input up to 2.5 Gbps to one up to 10Gbps, and serves them to the FPGA via the mezzanine connector. The board itself is controlled by a small FPGA by Two Wire Interface (TWI) protocol as a standalone intelligent device, with minimum slow control needed. An associated firmware has been developed to de-aggregate the data in the FPGA and recover the original digitalized data, with the JESD204 cores, inside the FPGA. The method has been validated and applications, beyond the development of the AGATA electronics, may be envisioned.

Primary authors

Dr COLLADO, Javier (Instituto de Física Corpuscular (IFIC) - CSIC / Universidad de Valencia - ETSE) Dr GONZALEZ, Vicente (Universidad de Valencia - ETSE) Dr GADEA, Andrés (Instituto de Física Corpuscular (IFIC) - CSIC)

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